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TSMC's 3DFabric Technology is the next big wave in Chip Design that Apple will take advantage of in the not-too-distant Future

1 x cover 3DFabric


In January Patently Apple posted a report titled "TSMC's CEO confirms that 3nm Processors are on target for mass production in 2022 while Advancing 3DFabric Technology." TSMC's CEO CC Wei was quoted as stating, "We observe chiplets are becoming an industry trend. We are working with several customers on 3DFabric to enable chiplet architecture." Interesting enough, Apple's work on developing a chiplet design started in 2017. Apple was granted their first patent for their chiplet design in March 2021 while filing an update just last month.


Considering that Apple is likely one of the partners that TSMC stated that they were working with on 3DFabric chiplet technology, I wanted to at least provide a basic report on Apple's patent so that engineers and geeks could further explore it, knowing that Apple could further advanced their chip designs using chiplets in the not-too-distant future.


I first discovered this patent over the weekend in the European Patent Office's archive and then worked it back to its U.S. filing under continuation patent  20210159180 titled "High Density Interconnection using Fanout Interposer Chiplet.


Apple notes in their patent background that the current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming, and other mobile devices requires the integration of more performance and features into increasingly smaller spaces.


As a result, the input/output density of dies and number of dies integrated within a single package have increased significantly. Various 2.5D and 3D packaging solutions in particular have been proposed as multi-die packaging solutions to connect adjacent die within a single package.


Apple's patent covers semiconductor packages and methods of fabrication in which an interposer chiplet is utilized to interconnect multiple components. In an embodiment, a package includes a plurality of conductive pillars and one or more interposer chiplets embedded within an encapsulation layer, and electrically connected to terminals of a first and second components.


In an embodiment, a package includes a first and second components embedded within an encapsulation layer. A first plurality of the terminals of the first and second components is in electrical connection with a plurality of conductive bumps laterally adjacent to one or more interposer chiplets that are in electrical connection with a second plurality of terminals of the first and second components. In both embodiments, the one or more interposer chiplets interconnect the first and second components. In both embodiments, a redistribution layer (RDL) may optionally be located between the layer including the first and second components, and the layer including the interposer chiplet and optionally the plurality of conductive pillars.


In one aspect, the interposer chiplet includes fine pitch component-to-component routing while the optional RDL includes coarser pitch fan out routing for the package. In this manner, the cost and complexity of including fine pitch routing within the RDL can be avoided. Additionally, it is not necessary to include an interposer with through silicon vias (TSVs) within the package.


In another aspect, some embodiments describe packaging methods, which may have a positive effect on package yield. The packaging methods may also be compatible with packaging process sequences such as chip-on-wafer-on-silicon that commonly utilize a silicon interposer. Thus, the optional RDL and embedded interposer chiplet in accordance with embodiments can be manufactured with wafer level design rules, while replacing conventional interposers in a packaging sequence.


In another aspect, embodiments describe interposer chiplet configurations which may optionally include an integrated passive device, such as resistor, inductor, capacitor, etc. Various modifications and variations for integrating an interposer chiplet within a package are contemplated in accordance with embodiments. The packages may additionally include a backside RDL, combinations of the same or different components, and addition of a heat spreader, stiffener ring, or embedded active die.


In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the embodiments.


Apple's patent FIG. 7 below is a cross-sectional side view illustration of multi-component package including an embedded interposer chiplet and back side redistribution layer; FIG. 13 is a process flow of a method of forming a multi-component package including an interposer chiplet


2 Apple chiplet invention


For more details, review Apple's continuation patent number 20210159180. Considering it's a continuation patent, Apple added 20 new patent claims. You could compare the current added claims to the original 20 claims by reviewing the claims of the granted patent issued in March 2021.


Considering that this is a continuation patent, the timing of this chiplet to market is unknown at this time.


10.51XF - Continuation Patent Report Bar


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